1. Field of the Invention
The present invention generally relates to semiconductor devices and, more particularly, to methods for fabricating a nonvolatile memory device.
2. Background of the Related Art
Generally, semiconductor memory devices are divided into volatile memories and nonvolatile memories. The volatile memories, including chiefly random access memories (RAM) such as dynamic random access memories (DRAM) and static random access memories (SRAM), retain their memory data when the power is turned on, but lose the stored data when the power is turned off. In contrast, the nonvolatile memories, including chiefly read only memories (ROM), retain their memory data even after the power is turned off.
The nonvolatile memories may be subdivided into ROM, programmable ROM (PROM), erasable PROM (EPROM), and electrically erasable PROM (EEPROM).
From the view point of process technology, the nonvolatile memories may be divided into a floating gate family and a metal insulator semiconductor (MIS) family comprising a multi-layer of two or more dielectrics. The memory devices of the floating gate family use potential wells to achieve memory characteristics. For instance, EPROM tunnel oxide (ETOX) structure and split gate structure are widely applied to flash EEPROM. The split gate structure comprises two transistors in one cell. On the other hand, the memory devices of the MIS family perform memory functions by using traps positioned on a bulk dielectric, the interface between dielectrics, and the interface between the dielectric and the semiconductor. At present, the MONOS (metal oxide nitride oxide semiconductor)/SONOS (semiconductor oxide nitride oxide semiconductor) structure is chiefly being employed for flash EEPROM.
FIG. 1 is a cross-sectional view of a flash memory cell structure formed by using a conventional technology. Referring to FIG. 1, a gate oxide layer 12 is deposited on a semiconductor substrate 10 having at least one device isolation layer 11. A first polysilicon layer 13 is deposited on the gate oxide layer 12. The first polysilicon layer 13 is used as a floating gate. A dielectric layer 15 and a second polysilicon layer 16 are sequentially deposited on the first polysilicon layer 13. The second polysilicon layer 16 is used as a control gate. A metal layer 17 and a nitride layer 18 are sequentially deposited on the second polysilicon layer 16. A cell structure is patterned to complete a flash memory cell by removing some portion of the gate oxide layer 12, the first polysilicon layer 13, the dielectric layer 15, the second polysilicon layer 16, the metal layer 17, and the nitride layer 18.
For a conventional process of fabricating a NOR flash memory, a self-aligned source (SAS) process or a self-aligned shallow trench isolation (SA-STI) process is chiefly adopted to minimize the unit cell area of the NOR flash memories. Although the SAS or the SA-STI process or even both processes are applied, the unit cell area cannot be reduced down to 4F2 (F is the minimum feature size of the manufacturing process), the minimum area of a NANA flash cell, because a bit line contact should be formed. Moreover, in fabricating a device with 2 bit sidewall floating gates, bit line contacts have to be formed on source and drain regions to form bit lines. Therefore, an additional area is required to form the bit line contacts. As a result, a cell structure without a bit line contact should be developed to minimize the unit cell area.